As semiconductor devices become highly integrated, not only do the sizes of patterns formed on a chip decrease, but the interval therebetween also decreases. At one time, polysilicon was a useful material as an interconnection material such as between gate electrodes and word lines. However, as the size of patterns decreases, resistivity of the polysilicon may become too high, resulting in resistive-capacitive (RC) time delay and voltage (IR) drop. Further, to improve a short-channel effect and punch-through caused by a reduction in gate length of a transistor, the junction depth of source and drain regions may be reduced, and simultaneously, parasitic resistance of the source and drain regions, for example, sheet resistance and contact resistance, may be reduced.